The present invention relates to semiconductor design technologies; and, more particularly, to a column address enable signal generation circuit for a semiconductor memory device. More specifically, the present invention is directed to a column address enable signal generation circuit for use in a semiconductor memory device, which is capable of adjusting the pulse width of a column address enable signal to be equivalent to that of an external clock applied to the memory device.
Generally, in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a read path for outputting data stored in cells is as follows.
First, a plurality of cells belonging to a word line WL selected by a row address selection signal is amplified by a bit line sense amp (BLSA).
Next, any one of a plurality of bit lines BLs connected to each of the cells amplified is selected by a column address selection signal.
Data carried on the selected bit line BL is outputted by passing through a segment input/output line SIO, a local input/output line (LIO) and a global input/output line GIO. And, data carried on the global input/output line GIO is provided to the outside of the semiconductor memory device through a data pad DQ.
As in the read path of DRAM set forth above, the column address selection signal is used to select any one of the plurality of bit lines BLs included in the selected word line WL when performing the write or read operation in which DRAM carries data on the bit line BL or takes it therefrom.
Therefore, it is necessary that the column address signal be activated by sensing the time when such a write or read operation to carry data on the bit line BL or take it therefrom is to be done.
A column address enable signal controls the activation and inactivation of the column address selection signal. A circuit for generating such a column address enable signal is given below.
FIG. 1 is a circuit diagram showing a conventional column address enable signal generation circuit used in a semiconductor memory device.
Referring to FIG. 1, the conventional column address enable signal generation circuit is provided with a column access signal output circuit 100 for outputting a column access signal CSA in response to a plurality of column access operation mode enable signals IRDP, IWTP, and CASP, a first rising edge sensor 102 for sensing a rising edge of the column access signal CSA, a second rising edge sensor 104 for sensing a rising edge of a return signal RET, a column address enable signal output circuit 106 for outputting a column address enable signal YAE that is activated in response to an output signal of the first rising edge sensor 102 and inactivated in response to an output signal of the second rising edge sensor 104, and a delay circuit 108 for taking and delaying a feedback signal FDB from the column address enable signal output circuit 106 by a preset time period to provide a delayed signal as the return signal RET.
The operation of the conventional column address enable signal generation circuit will now be described on the basis of the above-mentioned configuration.
First of all, when the column access signal CSA is activated in response to activation of any one of the plurality of column access operation mode enable signals IRDP, IWTP and CASP, it is the time that the column address enable signal YAE should be activated.
Therefore, the first rising edge sensor 102 senses a rising edge of the column access signal CSA, and outputs a signal having a very short preset activation time of, e.g., 1 ps (10−12 sec), and being toggled.
In response to the toggling of the signal from the first rising edge sensor 102, the column address enables signal output circuit 106 activates the column address enables signal YAE.
At the same time, the feedback signal FDB from the column address enable signal output circuit 106 is also activated and delayed by a preset sufficient time period of, e.g., 1 ns (10−9 sec), set by the delay circuit 108, and then provided as the return signal RET.
In addition, a rising edge of the return signal RET activated is sensed by the second rising edge sensor 104 which outputs a signal having a very short preset activation time of, e.g., 1 ps, and being toggled.
In response to the toggling of the signal from the second rising edge sensor 104, the column address enables signal output circuit 106 to inactivate the column address enables signal YAE.
In other words, the column address enable signal YAE is activated in response to activation of any one of the plurality of column access operation mode enable signals IRDP, IWTP and CASP, and inactivated after maintaining the activation interval for a preset time period set by the delay circuit 108 immediately after activation.
Therefore, the above-discussed column address signal generation circuit outputs the column address enable signal YAE having a constant activation interval. In other words, a column address selection signal has a constant pulse width.
By the way, the pulse width of the column address selection signal means a time period for which data is transmitted and received between the bit line BL and the local input/output line LIO for the write or read operation in a DRAM.
Therefore, if the pulse width of the column address selection signal is wide, it means that data can be transmitted and received for a sufficient time period between the bit line BL and the local input/output line LIO for the write or read operation in the DRAM.
However, this implies that a TAA time is long, wherein the TAA time denotes a time for which the DRAM can most quickly process a series of operations until the result is outputted in response to a read or write command of data inputted thereto.
On the contrary, if the pulse width of the column address selection signal is narrow, the TAA time is advantageous, while the time for which data is transmitted and received between the bit line BL and the local input/output line LIO is reduced.
Like this, the time for which data can be transmitted and received between the bit line BL has a trade-off relationship with the local input/output line LIO and the TAA time, which are dependent on the pulse width of the column address selection signal.
Thus, the data input/output operation of the DRAM can be stabilized only when the pulse width of the column address selection signal has a suitable pulse width that matches an operating frequency of an external clock provided from the outside of the DRAM.
However, the conventional column address enable signal generation circuit described referring to FIG. 1 provides the column address selection signal having a constant pulse width.
If the pulse width of the column address selection signal having a constant pulse width as above is determined for high frequency operation of DRAM, the time for which data is transmitted and received between the bit line BL and the local input/output line LIO is reduced, which may cause a timing mismatch in the DRAM that operates at a low frequency.
On the contrary, if the pulse width of the column address selection signal having a constant pulse width is determined for low frequency operation of the DRAM, the TAA time of the DRAM is lengthened, which may raise fail of data input/output in the DRAM that operates at a high frequency.